The high-speed Static Random Access Memory uses common input and output lines to simplify layout. There is an output enable pin which operates faster than address access time at read cycle so there is no los of speed.
The Memory allows that lower and upper byte access by data byte control(UB, LB).
The device is fabricated using advanced CMOS process, 6-TR based cell technology for reliable and cost effective performance, ideally suited for high-speed circuit technology.
The Memory is packaged in industry standard packages.
